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 HV7620 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs
Ordering Information
Package Options Device HV76 64 Pin Plastic Gullwing HV7620PG 80-Lead Ceramic Gullwing HV7620DG Die in Wafer Form HV7620XW
Features
Processed with HVCMOS(R) technology 5V CMOS logic and 12V supply rail Output voltage up to 200V Low power level shifting Source/sink current minimum 50mA 40MHz equivalent data rate Chip select Polarity function Forward and reverse shifting options (DIR pin) Latched outputs
General Description
The HV76 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has 4 parallel 8-bit shift registers permitting data rate 4 times the speed of one. The data are clocked in simultaneously on all four data inputs with a single clock. Data are shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data when connected to VDD1, and counterclockwise (CCW) shifting when connected to GND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open.
Absolute Maximum Ratings
Supply voltage1, VDD1 Supply voltage , VDD2 Supply voltage1, VPP Logic input levels1 Continuous total power dissipation Operating temperature range Storage temperature range
Notes: 1. All voltages are referenced to GND. 2. For operation above 25C ambient derate linearly to maximum operating temperature at 20mW/C for plastic and at 19mW/C for ceramic. 02/96/022
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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-0.5V to +15V -0.5V to +15V -0.5V to +225V -2.0V to VDD1+2.0V Plastic Ceramic Plastic Ceramic 1200mW 1900mW -40C to +85C -55C to 125C -65C to +150C
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HV7620
Electrical Characteristics (over recommended operating conditions unless noted)
DC Characteristics (VDD1 = 5V, VDD2 = 12V, VPP = 200V and TA = 25C)
Symbol IDD1 IDD2 IPP IDD1Q IDD2Q VOH VOL IIH IIL VGG Parameters VDD1 supply current VDD2 supply current High voltage supply current Quiescent VDD1 supply current Quiescent VDD2 supply current High-level output Low-level output High-level logic input current Low-level logic input current HVGND to LVGND voltage difference -1.0 185 20 1.0 -10 1.0 Min Max 5 20 2 100 100 Units mA mA mA A A V V A A V Condition fCLK =10MHz VDD2 = VDD2 max fCLK = 10 MHz All output high or low All input = VDD1 All input = VDD1 IO = -50mA IO = 50mA VIN = VDD1 VIN = 0V
AC Characteristics (Logic signal inputs and data inputs have tr, tf 5ns. VDD1 = 5V or 12V, VDD2 = 12V, VPP = 200V)
Symbol fCLK tWL, tWH tSU tH tON, tOFF tWLE tDLE tSLE tDLF, tDLN tCOF, tCON tDLH tDHL Parameters Clock frequency Clock width high or low Data set-up time Data hold time Time from LE to HVOUT Width of LE pulse Delay time clock to LE low to high LE setup time before clock rises BL or CS low to high to HVOUT Clock to HVOUT Delay time clock to data low to high Delay time clock to data high to low 25 50 20 250 275 100 100 VDD1 = 5V VDD1 = 12V 40 20 20 275 Min Max 10 5 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns CL = 15pF CL = 15pF CL = 15pF Condition Per register CL = 15pF Per register CL = 15pF
Recommended Operating Conditions
Symbol VDD1 VDD2 VPP VIH VIL fCLK TA IOD IGND(Vpp) VPP(SLEW)2 Parameters Logic supply voltage 12V supply voltage High voltage supply voltage High-level input voltage Low-level input voltage Clock frequency Operating free-air temperature Allowable pulsed current through ouptut diodes1 Allowable pulsed VPP or HVGND current1 Slew rate of VPP VDD1 = 5V VDD1 = 12V Plastic Ceramic -40 -55 Min 4.5 10.8 50 VDD1-0.5V 0 Max VDD2 13.2 200 VDD1 0.5 10 5 +85 +125 500 16 340 Unit V V V V V MHz MHz C C mA A V/s
Notes: 1.The current pulse width = 500ns, duty cycle = 5%. 2.This device cannot be hot-switched for output frequency greater than 500Hz. For output frequency greater than 500Hz, VPP must be ramped.
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HV7620
Input and Output Equivalent Circuits
VDD2 VDD1 VDD1 VPP
Input
DATA OUT
HVOUT
LVGND Logic Inputs
LVGND Logic Data Output
HVGND High Voltage Outputs
Switching Waveforms
V IH Data Input 50% t SU CLK
50% 50%
Data Valid tH
50% V IL tf
90% 50%
tr
90% 50%
V IH V IL V OH
10%
10%
t WL
t WH
t DLH Data Output t DHL
50%
V OL V OH
50%
V OL
50%
50%
V IH V IL
LE t DLE t COF HVOUT t WLE
90%
t SLE V OH V OL
t OFF V OH HVOUT
10%
t ON t CON
V OL
BLA, BLB, BLC, BLD, or CS t DLF HVOUT t DLN
90% 10%
V IH V IL V OH V OL
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HV7620
Functional Block Diagram
DINA DOUTA CLK
QA1 8-bit shift register 8-bit latches QA8
LE
BLA CS
POL HVOUT A1
BLB
HVOUT B1 HVOUT C1 HVOUT D1
8
DINB DOUTB
QB1 8-bit shift register 8-bit latches QB8
DIR
8
BLC
DINC DOUTC
QC1 8-bit shift register 8-bit latches QC8
8
BLD
HVOUT A8 HVOUT B8 HVOUT C8 HVOUT D8
DIND DOUTD
QD1 8-bit shift register 8-bit latches QD8
8
Function Table
Inputs Function DINA DINB DINC DIND CLK LE DIR BLA BLB BLC BLD CS POL A HV Outputs B C D
All O/P High All O/P Low "A" Outputs Low Normal Polarity Outputs Inverted Transparent Mode Data Stored Shift CW
X X X X X H X X
X X X X X L X X
X X X X X L X X
X X X X X L X X
X X X X X X
X X X X X H L H
X X X X X X X H
X X L H H H H H
X X X H H H H H
X X X H H H H H
X X X H H H H H
L L X H H H H H
L H H H L H H X
H L L
H L *
H L *
H L *
No Inversion Inversion H L L L
Stored Data AN A AN A BN B BN B CN C CN C DN D DN D
N+1
N+1
N+1
N+1
Shift CCW
X
X
X
X
H
L
H
H
H
H
H
X
N-1
N-1
N-1
N-1
Notes: H = High level, L = Low level, X = Irrelevant, = Low to high transition. * = Dependent on previous stage's state before the last CLK for last LE high. Power-up sequence: GND (HV, LV) VDD2 VDD1 Logic Input Signals VPP To power down reverse the sequence above. The VPP should not drop below VDD or float during operation.
4
HV7620
Pin Configurations
HV76 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function HVGND VPP HVOUTD8 HVOUTC8 HVOUTB8 HVOUTA8 HVOUTD7 HVOUTC7 HVOUTB7 HVOUTA7 HVOUTD6 HVOUTC6 HVOUTB6 HVOUTA6 HVOUTD5 HVOUTC5 HVOUTB5 HVOUTA5 VPP HVGND HVGND VDD2 BLC BLD LE DOUTD DIND DINC DOUTC POL LVGND DIR Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Function CS DOUTB DINB DINA DOUTA CLK BLA BLB VDD1 LVGND N/C HVGND HVGND VPP HVOUTD4 HVOUTC4 HVOUTB4 HVOUTA4 HVOUTD3 HVOUTC3 HVOUTB3 HVOUTA3 HVOUTD2 HVOUTC2 HVOUTB2 HVOUTA2 HVOUTD1 HVOUTC1 HVOUTB1 HVOUTA1 VPP HVGND
Package Outline
1
Index
64
24 25 top view 40
41
3-sided Plastic 64-pin Gullwing Package
64 65
41 40
Index 80 1 top view 24 25
*Pins 65 to 80 are N/C (ceramic only)
80-pin Ceramic Gullwing Package
02/06//02
(c)2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
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1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 * FAX: (408) 222-4895 www.supertex.com


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